semiconductor technical data order this document by mpc990/d 1 rev 3 ? motorola, inc. 1999 1/99 the mpc990/991 is a 3.3v compatible, pll based ecl/pecl clock driver. the fully differential design ensures optimum skew and pll jitter performance. the performance of the mpc990/991 makes the device ideal for workstation, mainframe computer and telecommunication applications. the mpc990 and mpc991 devices are identical except in the interface to the reference clock for the pll. the mpc990 offers an onboard crystal oscillator as the pll reference while the mpc991 offers a differential ecl/pecl input for applications which need to lock to an existing clock signal. both designs offer a secondary singleended ecl clock for system test capabilities. ? fully integrated pll ? output frequency up to 400mhz ? ecl/pecl inputs and outputs ? operates from a 3.3v supply ? output frequency configurable ? tqfp packaging ? 50ps cycletocycle jitter the mpc990/991 offers three banks of outputs which can each be programmed via the the four fsel pins of the device. there are 16 different output frequency configurations available in the device. the configurations include output ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 4:3:1 and 4:3:2. the programming table in this data sheet illustrates the various programming options. the sync output monitors the relationship between the qa and qc output banks. the output pulses per the timing diagrams in this data sheet signal the coincident edges of the two output banks. this feature is useful for non binary relationships between output frequencies (i.e., 3:2 or 4:3 relationships). the sync_sel input toggles the qd outputs between sync signals and extensions to the qc bank of outputs. the mpc990/991 provides a separate output for the feedback to the pll. this allows for the feedback frequency to be programmed independently of the other outputs allowing for unique input vs output frequency relationships. the fselfb inputs provide 6 different feedback frequencies from the qfb differential output pair. the mpc990/991 features an external differential ecl/pecl feedback to the pll. this external feedback feature allows for the mpc991's use as a azeroo delay buffer. the propagation delay between the input reference and the output is dependent on the input reference frequency. the selection of higher reference frequencies will provide near zero delay through the device. the pll_en, ref_sel and the test_clk input pins provide a means of bypassing the pll and driving the output buffers directly. this allows the user to single step a design during system debug. note that the test_clk input is routed through the dividers so that depending on the programming several edges on the test_clk input will be needed to get corresponding edge transitions on the outputs. the vco_sel input provides a means of recentering the vco to provide a broader range of vco frequencies for stable pll operation. if the frequency select or the vco_sel pins are changed during operation, a master reset signal must be applied to ensure output synchronization and phaselock. if the vco is driven beyond its maximum frequency, the vco can outrun the internal dividers when the vco_sel pin is low. this will also prevent the pll from achieving lock. again, a master reset signal will need to be applied to allow for phaselock. the device employs a poweron reset circuit which will ensure output synchronization and pll lock on initial powerup. low voltage pll clock driver fa suffix 52lead tqfp package case 848d03
mpc990 mpc991 motorola timing solutions br1333 e rev 6 2 qfb qfb vcco qd0 qd0 qd1 qd1 vcco qc0 qc0 qc1 qc1 vcca fsel0 qb2 qb2 fsel1 qb1 qb1 fsel2 qb0 qb0 vcco qc2 qc2 fsel3 gndi mr pll_en ref_sel fselfb2 fselfb1 fselfb0 test_clk vcci ext_fb xtal1 (990) xtal2 (990) ext_fb 40 41 42 43 44 45 46 47 48 49 50 51 52 25 24 23 22 21 20 19 18 17 16 15 14 12345678910111213 39 38 37 36 35 34 33 32 31 30 29 28 27 26 mpc990/ mpc991 ecl_clk (991) ecl_clk (991) vco_sel sync_sel qa3 qa3 qa2 qa2 qa1 qa1 qa0 qa0 vcco qb3 qb3 figure 1. 52lead pinout (top view) function table 1 inputs outputs fsel3 fsel2 fsel1 fsel0 qa qb qc 0 0 0 0 2 2 2 0 0 0 1 2 2 4 0 0 1 0 2 4 4 0 0 1 1 2 2 6 0 1 0 0 2 6 6 0 1 0 1 2 4 6 0 1 1 0 2 4 8 0 1 1 1 2 6 8 1 0 0 0 2 2 8 1 0 0 1 2 8 8 1 0 1 0 4 4 6 1 0 1 1 4 6 6 1 1 0 0 4 6 8 1 1 0 1 6 6 8 1 1 1 0 6 8 8 1 1 1 1 8 8 8
mpc990 mpc991 timing solutions br1333 e rev 6 3 motorola function table 2 fselfb2 fselfb1 fselfb0 qfb 0 0 0 0 0 0 1 1 0 1 0 1 2 4 6 8 1 1 1 1 0 0 1 1 0 1 0 1 8 16 24 32 function table 3 control pin logic `0' logic `1' pll_en enable pll bypass pll vco_sel fvco fvco/2 ref_sel xtal or ecl/pecl test_clk mr e reset outputs sync_sel sync outputs match qc outputs figure 2. mpc990/991 logic diagram vco phase detector lpf pll_en vco_sel ecl_clk ecl_clk test_clk ref_sel ext_fb ext_fb qa0 qa0 qa1 qa1 qa2 qa2 qa3 qa3 qb0 qb0 qb1 qb1 qb2 qb2 qb3 qb3 qc0 qc0 qc1 qc1 qc2 qc2 qd0 qd0 qd1 qd1 qfb qfb frequency generator sync mr fsela0:3 fselfb0:2 sync_sel (pulldown) (pulldown) (pulldown) (pulldown) (pulldown) (pulldown) (pulldown) (pulldown) mpc991 mpc990 xtal osc note: ecl_clk, ext_fb have internal pulldowns, while ecl_clk , ext_fb have external pullups to ensure stability under open input conditions.
mpc990 mpc991 motorola timing solutions br1333 e rev 6 4 figure 3. timing diagrams qa 1:1 mode qc sync (qd) v cc qa 2:1 mode qc sync (qd) qa 3:1 mode qc sync (qd) qa 3:2 mode qc sync (qd) qa 4:3 mode qc sync (qd)
mpc990 mpc991 timing solutions br1333 e rev 6 5 motorola ecl dc characteristics (t a = 0 to 70 c, v cca = v cci = v cco = 0v, gndi = 3.3v 5%, note 1.) 0 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit v oh output high voltage 1.3 0.7 1.3 1.0 0.7 1.3 0.7 v v ol output low voltage 2.0 1.4 2.0 1.7 1.4 2.0 1.4 v v ih input high voltage 1.1 0.9 1.1 0.9 1.1 0.9 v v il input low voltage 1.8 1.5 1.8 1.5 1.8 1.5 v v pp minimum input swing 500 500 500 mv v cmr common mode range v cc 1.3v v cc 0.5v v cc 1.3v v cc 0.5v v cc 1.3v v cc 0.5v v i ih input high current 150 150 150 m a i gndi power supply current 200 240 200 240 200 240 ma 1. refer to motorola application note an1545/d a thermal data for mpc clock drivers o for thermal management guidelines. pecl dc characteristics (t a = 0 to 70 c, v cca = v cci = v cco = 3.3v 5%, gndi = 0v, note 2.) 0 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit v oh output high voltage (note 3.) 2.0 2.6 2.0 2.3 2.6 2.3 2.6 v v ol output low voltage (note 3.) 1.3 1.9 1.3 1.6 1.9 1.3 1.9 v v ih input high voltage (note 3.) 2.2 2.4 2.2 2.4 2.2 2.4 v v il input low voltage (note 3.) 1.5 1.8 1.5 1.8 1.5 1.8 v v pp minimum input swing 500 500 500 mv v cmr common mode range v cc 1.3v v cc 0.5v v cc 1.3v v cc 0.5v v cc 1.3v v cc 0.5v v i ih input high current 150 150 150 m a i gndi power supply current 200 240 200 240 200 240 ma 2. refer to motorola application note an1545/d a thermal data for mpc clock drivers o for thermal management guidelines. 3. these values are for v cc = 3.3v. level specifications will vary 1:1 with v cc . ac characteristics (t a = 0 to 70 c, v cca = v cci = v cco = 3.3v 5%, termination of 50 w to v cc 2.0v) symbol characteristic min typ max unit condition f xtal crystal oscillator frequency 10 25 mhz t r , t f output rise/fall time 0.2 1.0 ns 20% to 80% t pw output duty cycle 47.5 50 52.5 % t os output-to-output skew same frequency different frequencies 150 250 250 350 ps f vco pll vco lock range vco_sel = `0' vco_sel = `1' 400 200 800 400 mhz fb 8 to 32 (note 4.) fb 4 to 32 t pd ref to feedback offset 75 250 425 ps f ref = 50mhz (note 5.) f max maximum output frequency qa,qb,qc ( 2) qa,qb,qc ( 4) qa,qb,qc ( 6) qa,qb,qc ( 8) 400 200 133 100 mhz t jitter cycletocycle jitter (peaktopeak) 50 ps t lock maximum pll lock time 10 ms 4. with vco_sel = `0', the pll will be unstable with a 2, 4 and some 6 feedback configurations. with vco_sel = `1', the pll will be unstable with a 2 feedback ratio. 5. t pd is specified for 50mhz input reference fb 8. the window will shrink/grow proportionally from the minimum limit with shorter/longer input reference periods. the t pd does not include jitter.
mpc990 mpc991 motorola timing solutions br1333 e rev 6 6 pll input reference characteristics (t a =0 to 70 c) symbol characteristic min max unit condition t r , t f tclk input rise/falls 3.0 ns f ref reference input frequency feedback divide 6 vco_sel='0' feedback divide 8 feedback divide 16 feedback divide 24 feedback divide 32 100 50 25 16.67 12.5 125 100 50 33.33 25 mhz vco_sel='1' feedback divide 4 feedback divide 6 feedback divide 8 feedback divide 16 feedback divide 24 feedback divide 32 50 33.3 25 12.5 8.33 6.25 100 66.67 50 25 16.67 12.5 f refdc reference input duty cycle 25 75 % applications information using the onboard crystal oscillator the mpc990 features an onboard crystal oscillator to allow for seed clock generation as well as final distribution. the onboard oscillator is completely self contained so that the only external component required is the crystal. as the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the mpc990 as possible to avoid any board level parasitics. to facilitate colocation surface mount crystals are recommended, but not required. the oscillator circuit is a series resonant circuit as opposed to the more common parallel resonant circuit, this eliminates the need for large onboard capacitors. because the design is a series resonant design for the optimum frequency accuracy a series resonant crystal should be used (see specification table below). unfortunately most of the shelf crystals are characterized in a parallel resonant mode. however a parallel resonant crystal is physically no different than a series resonant crystal, a parallel resonant crystal is simply a crystal which has been characterized in its parallel resonant mode. therefore in the majority of cases a parallel specified crystal can be used with the mpc990 with just a minor frequency error due to the actual series resonant frequency of the parallel resonant specified crystal. typically a parallel specified crystal used in a series resonant mode will exhibit an oscillatory frequency a few hundred ppm lower than the specified value. for most processor implementations a few hundred ppm translates into khz inaccuracies, a level which does not represent a major issue. the mpc990 is a clock driver which was designed to generate outputs with programmable frequency relationships and not a synthesizer with a fixed input frequency. as a result the crystal input frequency is a function of the desired output frequency. for a design which utilizes the external feedback to the pll the selection of the crystal frequency is straight forward; simply chose a crystal which is equal in frequency to the fed back signal. table 1. crystal specifications parameter value crystal cut fundamental at cut resonance series resonance* frequency tolerance 75ppm at 25 c frequency/temperature stability 150pm 0 to 70 c operating range 0 to 70 c shunt capacitance 57pf equivalent series resistance (esr) 50 to 80 w max correlation drive level 100 m w aging 5ppm/yr (first 3 years) * see accompanying text for series versus parallel resonant discussion. power supply filtering the mpc990/991 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. the mpc990/991 provides separate power supplies for the output buffers (v cco ) and the internal pll (vcca) of the device. the purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phaselocked loop. in a controlled environment such as an evaluation board this level of isolation is sufficient. however, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. the simplest form of isolation is a power supply filter on the vcca pin for the mpc990/991. figure 4 illustrates a typical power supply filter scheme. the mpc990/991 is most susceptible to noise with spectral content in the 1khz to 1mhz range. therefore the filter
mpc990 mpc991 timing solutions br1333 e rev 6 7 motorola should be designed to target this range. the key parameter that needs to be met in the final filter design is the dc voltage drop that will be seen between the v cc supply and the vcca pin of the mpc990/991. from the data sheet the i vcca current (the current sourced through the vcca pin) is typically 15ma (20ma maximum), assuming that a minimum of 3.0v must be maintained on the vcca pin very little dc voltage drop can be tolerated when a 3.3v v cc supply is used. the resistor shown in figure 4 must have a resistance of 515 w to meet the voltage drop criteria. the rc filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20khz. as the noise frequency crosses the series resonant point of an individual capacitor it's overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. although the mpc990/991 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential pll) there still may be applications in which overall performance is being degraded due to system power supply noise. the power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. figure 4. power supply filter vcca vcc mpc990/991 0.01 m f 22 m f 0.01 m f 3.3v r s =515 w
mpc990 mpc991 motorola timing solutions br1333 e rev 6 8 outline dimensions fa suffix tqfp package case 848d-03 issue d f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums l, m and n to be determined at datum plane h. 5. dimensions s and v to be determined at seating plane t. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the lead width to exceed 0.46 (0.018). minimum space between protrusion and adjacent lead or protrusion 0.07 (0.003). ???? ???? view aa view aa 2 x r r1 ab ab view y section abab rotated 90 clockwise dim a min max min max inches 10.00 bsc 0.394 bsc millimeters a1 5.00 bsc 0.197 bsc b 10.00 bsc 0.394 bsc b1 5.00 bsc 0.197 bsc c 1.70 0.067 c1 0.05 0.20 0.002 0.008 c2 1.30 1.50 0.051 0.059 d 0.20 0.40 0.008 0.016 e 0.45 0.030 f 0.22 0.35 0.009 0.014 g 0.65 bsc 0.75 0.018 0.026 bsc j 0.07 0.20 0.003 0.008 k 0.50 ref 0.020 ref r1 0.08 0.20 0.003 0.008 s 12.00 bsc 0.472 bsc s1 6.00 bsc 0.236 bsc u 0.09 0.16 0.004 0.006 v 12.00 bsc 0.472 bsc v1 6.00 bsc 0.236 bsc w 0.20 ref 0.008 ref z 1.00 ref 0.039 ref c l x x=l, m, n 1 13 14 26 27 39 40 52 4x tips 4x n 0.20 (0.008) h lm n 0.20 (0.008) t lm 3x view y seating plane c 0.10 (0.004) t 4x q 3 4x q 2 s 0.05 (0.002) 0.25 (0.010) gage plane c2 c1 w k e z s lm m 0.13 (0.005) n s t plating base metal d j u b v b1 a s v1 a1 s1 l n m h t q 1 q g q 1 q q 3 q 2 07 12 513 07 0 0 ref 12 ref 13 5
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